1. Field of the Invention
The present invention pertains to the field of pulse modulators and demodulators using the delta modulation system.
2. Description of the Related Art
Delta modulation, a one bit pulse-code modulation scheme for digitizing an analog signal, and the National Television Standards Committee (NTSC) video signal are well-known and will be briefly reviewed as background for the present invention. In Delta modulation each bit represents the desired instantaneous slope of a signal which is the integrated encoded signal and corresponds to the input analog signal. Typically, a "one" of the encoded signal represents a positive slope and a "zero" represents a negative slope. In a delta modulation encoder or modulator, the modulated output signal is provided to an integrating circuit whose output is compared at each bit time to the input analog signal to determine the next output bit of a non-return- to-zero (NRZ) modulated signal. A basic delta modulation encoder consists of a flip-flop to generate the bits at times determined by any suitable clock signal, a RC circuit having a time constant much longer than each bit time to perform the integration, and a comparator receiving the analog signal and the integrating circuit output. The comparator output is arranged to set or reset the flip-flop so that the resulting slope of the integrated signal is in a direction to correct any difference between the integrated signal and the input signal. A delta modulation decoder or demodulator receives the modulated signal and any necessary clock signal and consists only of an integrating circuit which is substantially identical to that of the encoder and thus reconstructs the original analog signal. In telemetry the clock signal may be provided at the decoder in a well- known manner by a phase locked circuit controlled by transitions in the modulated signal.
As the NRZ delta modulated signal is integrated, the integrated signal will always have a slope or slew rate determined by the integrator time constant. As a result, a constant analog signal to the encoder is represented by alternate ones and zeroes in the modulated signal and by segments of the reconstructed signal alternating upwardly and downwardly by such slope. However, it is apparent that an original analog signal having variations corresponding to lesser changes than the changes in such an encoded constant signal will also be decoded as a constant; this is termed "quantizing error". It is also apparent that, conversely, an original signal having variations greater than such slope cannot be followed by the integrator; this condition is termed "slope overload". These limitations of delta modulation may be alleviated by increasing the bit rate, but the bit rate cannot, of course, be increased arbitrarily and without limit.
As a result, it is well-known to provide arrangements for delta modulation in which such slope is varied by changing the time constant of the integrating RC circuit in some manner so that such slope is low to minimize quantizing error when alternate ones and zeroes in the modulated signal indicate the encoder is following the input signal and so that such slope is increased when successive ones or zeroes in the modulated signal indicate the signal represented by the encoder output is lagging the input signal. Such arrangements and modulation are thus referred to herein as "multi-slope delta modulation" or, since the slope may change each bit time, as "continuously variable slope delta modulation". Such delta modulation is also termed "high information delta modulation" or "adaptive delta modulation". It is well-known to use two or more such slopes selected by appropriate logic based on the values of successive bits.
Delta modulation is used extensively for voice transmission, where limited changes in amplitude at high voice frequencies minimize problems with quantizing error and slope overload. However, delta modulation has not been extensively applied to the NTSC video signal where quantizing error results in excessive "smearing" of the reproduced image in near identical gray areas, which are common in industrial and telemetered video images for reasons such as low light level, and where slope overload results from a rapid change in the signal at a white to black or black to white border or at the end of a video line when there is a transition between the maximum white level to the minimum or "sync" level. However, in comparison to other modulation schemes, very few elements using little power are required in a modulator or encoder for delta modulation so that delta modulation is highly desirable for certain telemetry applications where the telemetry transmitting elements must be compact, be light in weight, require low power, and be expendable. However, in these applications a great deal of other data must be telemetered in addition to a NTSC signal so that these constraints also limit the bandwidth and bit rate available for the NTSC signal.
A multi-slope delta modulation encoder representative of the prior art is shown in FIG. 1 and has an input 10 for an NTSC video signal to be encoded and has an output 11 for the encoded delta modulation signal. Elements and connections used with the encoder to provide a positive supply voltage, ground connections, and clock pulses are believed readily apparent to one skilled in the art and are omitted for clarity. The encoder has any suitable comparator 15 having a positive input 16, a negative input 17, and an output 18. Comparator 15 functions in a well-known manner to provide a positive level at output 18 when input 16 is at a relatively higher level than input 17 and to provide a negative level at output 18 when input 16 is at a relatively lower level than input 17. Encoder input 10 is connected to comparator input 16 through a 2 uf capacitor 19, a 75 ohm termination resistor 21 for the NTSC signal being connected between input 10 and ground. Any suitable voltage divider 22 is connected at comparator input 13 to center the signal thereat in the dynamic range of comparator 15. Comparator 15 may be a Linear Technology LT1016 comparator having a nominal delay time of 10 nsec for following the NTSC signal, divider 22 then consisting of a 4.42 Kohm resistor 23 connected between input 13 and a 5 volt source and of a 4.02 Kohm resistor 24 connected between this input and ground.
The encoder has a flip-flop 30 having an input 31 connected to comparator output a clock input 32, and an output 33 connected to encoder output 11 and set or reset to correspond to the output 18 level when a clock pulse is provided to input 32. The encoder has an integrating capacitor 35 having one side connected to ground and the other side connected to comparator input 17 by a conductor 37. The encoder has three resistors 41, 42, and 43 connected in parallel between output 11 and conductor 37. Resistor 41 is permanently connected between output 11 and conductor 37, and resistors 42 and 43 are connected therebetween through respective solid state switches 45 and 46.
The encoder has a pair of flip-flops 50 and 51 which are similar to flip-flop 30 and receive the same clock signal. The input of flip- flop 50 is connected to encoder output 11 so as to receive the current bit level thereon, and the input of flip-flop 51 is connected to the output of flip-flop 50. Flip-flop 50 thus retains the level of the bit provided by the encoder previous to the current bit while flip-flop 51 retains the level of the bit preceding such previous bit. The encoder has any suitable switch logic circuit 55 which, functionally, has a first exclusive-or gate 56 receiving the current bit output 11 and the previous bit output from flip-flop 50 and has a second exclusive-or gate 57 receiving the previous two bit output levels from flip-flops 50 and 51. The output of gate 56 controls switch 45 and is provided, together with the output from gate 57, to an AND gate 58 which controls switch 46.
It is evident from the connections of flip-flops 50 and 51 and circuit 55 that, when the current bit and the previous two bits output by the encoder are the same, switches 45 and 46 are closed and capacitor 35 charges rapidly through an equivalent resistance of 250 ohms to provide a steep slope for the signal on output 11. However, when the current and immediately previous bits are the same but different from the other retained bit, only switch 45 is closed and the capacitor charges through an equivalent resistance of 500 ohms to provide an intermediate slope. For other bit patterns, switches 45 and 46 are open so that the capacitor charges only through the 750 ohm resistor 41 to provide a minimum slope for the encoder output signal. It is apparent that, by selection of different resistances for resistors 41-43 and different arrangements of logic elements such as those of circuit 55, the signal on output 11 may have other slopes corresponding to other desired patterns of successive bits of this signal.
While an encoder such as that of FIG. 1 is effective as a multi-slope delta modulation encoder and is simpler than modulators for other forms of modulation, such an encoder has a number of elements, particularly the solid state switches and logic elements of circuit 55, which are relatively bulky and heavy, consume power, increase cost, and complicate circuit layout and construction.